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<title>VCVTPS2QQ—Convert Packed Single Precision Floating-Point Values to Packed Singed Quadword Integer Values </title></head>
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<h1>VCVTPS2QQ—Convert Packed Single Precision Floating-Point Values to Packed Singed Quadword Integer Values</h1>
<table>
<tr>
<th>Opcode/Instruction</th>
<th>Op /En</th>
<th>64/32 bit Mode Support</th>
<th>CPUID Feature Flag</th>
<th>Description</th></tr>
<tr>
<td>
<p>EVEX.128.66.0F.W0 7B /r</p>
<p>VCVTPS2QQ xmm1 {k1}{z}, xmm2/m64/m32bcst</p></td>
<td>HV</td>
<td>V/V</td>
<td>
<p>AVX512VL</p>
<p>AVX512DQ</p></td>
<td>Convert two packed single precision floating-point values from xmm2/m64/m32bcst to two packed signed quadword values in xmm1 subject to writemask k1.</td></tr>
<tr>
<td>
<p>EVEX.256.66.0F.W0 7B /r</p>
<p>VCVTPS2QQ ymm1 {k1}{z}, xmm2/m128/m32bcst</p></td>
<td>HV</td>
<td>V/V</td>
<td>
<p>AVX512VL</p>
<p>AVX512DQ</p></td>
<td>Convert four packed single precision floating-point values from xmm2/m128/m32bcst to four packed signed quadword values in ymm1 subject to writemask k1.</td></tr>
<tr>
<td>
<p>EVEX.512.66.0F.W0 7B /r</p>
<p>VCVTPS2QQ zmm1 {k1}{z}, ymm2/m256/m32bcst{er}</p></td>
<td>HV</td>
<td>V/V</td>
<td>AVX512DQ</td>
<td>Convert eight packed single precision floating-point values from ymm2/m256/m32bcst to eight packed signed quadword values in zmm1 subject to writemask k1.</td></tr></table>
<h3>Instruction Operand Encoding</h3>
<table>
<tr>
<td>Op/En</td>
<td>Operand 1</td>
<td>Operand 2</td>
<td>Operand 3</td>
<td>Operand 4</td></tr>
<tr>
<td>HV</td>
<td>ModRM:reg (w)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td>
<td>NA</td></tr></table>
<p><strong>Description</strong></p>
<p>Converts eight packed single-precision floating-point values in the source operand to eight signed quadword inte-gers in the destination operand.</p>
<p>When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR register or the embedded rounding control bits. If a converted result cannot be represented in the destination format, the floating-point invalid exception is raised, and if this exception is masked, the indefinite integer value (2<sup>w-1</sup>, where w represents the number of bits in the destination format) is returned.</p>
<p>The source operand is a YMM/XMM/XMM (low 64- bits) register or a 256/128/64-bit memory location. The destina-tion operation is a ZMM/YMM/XMM register conditionally updated with writemask k1.</p>
<p>Note: EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.</p>
<p><strong>Operation</strong></p>
<p><strong>VCVTPS2QQ (EVEX encoded versions) when src operand is a register</strong></p>
<p>(KL, VL) = (2, 128), (4, 256), (8, 512)</p>
<p>IF (VL == 512) AND (EVEX.b == 1)</p>
<p>THEN</p>
<p>SET_RM(EVEX.RC);</p>
<p>ELSE</p>
<p>SET_RM(MXCSR.RM);</p>
<p>FI;</p>
<p>FOR j (cid:197) 0 TO KL-1</p>
<p>i (cid:197) j * 64</p>
<p>k (cid:197) j * 32</p>
<p>IF k1[j] OR *no writemask*</p>
<p>THEN DEST[i+63:i] (cid:197)</p>
<p>Convert_Single_Precision_To_QuadInteger(SRC[k+31:k])</p>
<p>ELSE</p>
<p>IF *merging-masking*</p>
<p>; merging-masking</p>
<p>THEN *DEST[i+63:i] remains unchanged*</p>
<p>ELSE</p>
<p>; zeroing-masking</p>
<p>DEST[i+63:i] (cid:197) 0</p>
<p>FI</p>
<p>FI;</p>
<p>ENDFOR</p>
<p>DEST[MAX_VL-1:VL] (cid:197) 0</p>
<p><strong>VCVTPS2QQ (EVEX encoded versions) when src operand is a memory source</strong></p>
<p>(KL, VL) = (2, 128), (4, 256), (8, 512)</p>
<p>FOR j (cid:197) 0 TO KL-1</p>
<p>i (cid:197) j * 64</p>
<p>k (cid:197) j * 32</p>
<p>IF k1[j] OR *no writemask*</p>
<p>THEN</p>
<p>IF (EVEX.b == 1)</p>
<p>THEN</p>
<p>DEST[i+63:i] (cid:197)</p>
<p>Convert_Single_Precision_To_QuadInteger(SRC[31:0])</p>
<p>ELSE</p>
<p>DEST[i+63:i] (cid:197)</p>
<p>Convert_Single_Precision_To_QuadInteger(SRC[k+31:k])</p>
<p>FI;</p>
<p>ELSE</p>
<p>IF *merging-masking*</p>
<p>; merging-masking</p>
<p>THEN *DEST[i+63:i] remains unchanged*</p>
<p>ELSE</p>
<p>; zeroing-masking</p>
<p>DEST[i+63:i] (cid:197) 0</p>
<p>FI</p>
<p>FI;</p>
<p>ENDFOR</p>
<p>DEST[MAX_VL-1:VL] (cid:197) 0</p>
<p><strong>Intel C/C++ Compiler Intrinsic Equivalent</strong></p>
<p>VCVTPS2QQ __m512i _mm512_cvtps_epi64( __m512 a);</p>
<p>VCVTPS2QQ __m512i _mm512_mask_cvtps_epi64( __m512i s, __mmask16 k, __m512 a);</p>
<p>VCVTPS2QQ __m512i _mm512_maskz_cvtps_epi64( __mmask16 k, __m512 a);</p>
<p>VCVTPS2QQ __m512i _mm512_cvt_roundps_epi64( __m512 a, int r);</p>
<p>VCVTPS2QQ __m512i _mm512_mask_cvt_roundps_epi64( __m512i s, __mmask16 k, __m512 a, int r);</p>
<p>VCVTPS2QQ __m512i _mm512_maskz_cvt_roundps_epi64( __mmask16 k, __m512 a, int r);</p>
<p>VCVTPS2QQ __m256i _mm256_cvtps_epi64( __m256 a);</p>
<p>VCVTPS2QQ __m256i _mm256_mask_cvtps_epi64( __m256i s, __mmask8 k, __m256 a);</p>
<p>VCVTPS2QQ __m256i _mm256_maskz_cvtps_epi64( __mmask8 k, __m256 a);</p>
<p>VCVTPS2QQ __m128i _mm_cvtps_epi64( __m128 a);</p>
<p>VCVTPS2QQ __m128i _mm_mask_cvtps_epi64( __m128i s, __mmask8 k, __m128 a);</p>
<p>VCVTPS2QQ __m128i _mm_maskz_cvtps_epi64( __mmask8 k, __m128 a);</p>
<p><strong>SIMD Floating-Point Exceptions</strong></p>
<p>Invalid, Precision</p>
<p><strong>Other Exceptions</strong></p>
<table>
<tr>
<td>EVEX-encoded instructions, see Exceptions Type E3</td></tr>
<tr>
<td>If EVEX.vvvv != 1111B.</td></tr></table></body></html>